Commodore computer

[Bernard Robertson-Dunn]

At the other end of the scale, a mainframe on a chip:
>From the EETimes,
http://www.eet.com/news/98/1023news/mainframe.html

IBM's mainframe chip takes the road less traveled

By Ron Wilson

PALO ALTO, Calif. - IBM principal architect Timothy Slegel described
what he called the world's fastest mainframe - the single-chip G5
System 390 CPU - at the 10th annual IEEE Computer Society Hot Chips
Conference earlier this week. In almost every respect it is the
architectural antithesis of the present RISC world.

The 390 instruction set is not reduced. The most common instruction
type takes one argument from a register and another from memory,
with a rich array of memory-addressing options. Some
memory-to-memory operations can act on thousands of words at a time.
And decimal arithmetic is still used heavily enough to require
optimization.

This mandates microcode. "A hardware 390 would never get out the
door," said Slegel. "You have to use microcode to make the
instruction set tractable."

Nor is the G5 superscalar. "With this instruction set, there is more
to be gained by making the memory/register instructions execute in a
single cycle than by trying to do multiple issue," Slegel said.

This concern even changes the cache architecture. Instead of the
conventional L1 instruction and data caches, the G5 uses a single,
unified L1 cache, interleaved to support the heavy traffic from the
memory-based instruction set.

But the biggest difference between the G5 and the current flock of
RISC processors lies in another area - reliability. "The chip has
totally duplicated instruction and execution units," Slegel said.
"The two sets of units compare results at the end of every cycle. If
there is no match, the chip enters a hardware-recovery mode,
completely transparent to the customer." The chip can correct
virtually any soft error transparently, and can recover from any
hard error without loss of the system.

In addition to the on-chip redundancy, the G5 is shipped in modules
of 18 CPUs each, many of which are redundant processors. In case of
a hard error in a CPU, a spare processor is switched in
transparently.

Such attention to reliability and availability still seems to be a
foreign concept in the world of RISC. However, as the desktop
architectures of the early 1990s move into mission-critical server
applications, they should take seriously the lessons from an
architecture that has been there, done that.

-- 
God is Real -- unless declared Integer
-- unknown, but probably a FORTRAN programmer

Regards
brd

Bernard Robertson-Dunn
Canberra Australia
brd@dynamite.com.au